Kishlay Singh holds an M.Tech in VLSI Design from the National Institute of Technology Delhi and is a researcher based in New Delhi, India, working in digital circuit design and low-power circuit design. His research centers on SRAM design and functional verification, with a particular interest in UVM-based verification methodologies, assertion-based verification, and fault injection techniques for memory architectures operating at near-threshold voltages. He focuses on building rigorous, reproducible verification approaches that improve the reliability of energy-efficient memory systems. He is actively preparing research for publication in IEEE conferences and journals, and he is keen to contribute to the peer-review community in electronic circuits and devices.
